AD9772A-EB datasheet(19/40 Pages) AD

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AD9772A

Rev. C | Page 19 of 40

Zero-Stuffing Option Description

As shown in Figure 29, a zero or null in the frequency response

(after interpolation and DAC reconstruction) occurs at the final

DAC update rate (that is, 2× fDATA) due to the inherent sin(x)/x

roll-off response of the DAC. In baseband applications, this roll-

off in the frequency response may not be as problematic

because much of the desired signal energy remains below

fDATA/2 and the amplitude variation is not as severe. However, in

direct IF applications interested in extracting an image above

fDATA/2, this roll-off may be problematic due to the increased

pass-band amplitude variation as well as the reduced signal

level of the higher images.

FREQUENCY (

fDATA)

–10

–40

4.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

–20

–30

WITH

ZERO-STUFFING

WITHOUT

ZERO-STUFFING

BASEBAND

REGION

Figure 29. Effects of Zero-Stuffing on the Sin(x)/x Response of the DAC

For instance, if the digital data into the AD9772A represents a

baseband signal centered around fDATA/4 with a pass band of

fDATA/10, the reconstructed baseband signal output from the

AD9772A experiences only a 0.18 dB amplitude variation over

its pass band, with the first image occurring at 7/4 × fDATA and

exhibiting 17 dB of attenuation relative to the fundamental.

However, if the high-pass filter response is selected, the AD9772A

produces pairs of images at [(2N + 1) × fDATA] ± fDATA/4, where

N = 0, 1, and so on. Note that due to the sin(x)/x response of the

DAC, only the lower or upper sideband images centered around

fDATA may be useful, although they are attenuated by −2.1 dB and

−6.54 dB and have a pass-band amplitude roll-off of 0.6 dB and

1.3 dB, respectively.

To improve on the pass-band flatness of the desired image

and/or to extract higher images (that is, 3 × fDATA ± fFUNDAMENTAL),

the zero-stuffing option should be employed by bringing the

MOD1 pin high. This option increases the effective DAC

update rate by another factor of 2 because a midscale sample

(that is, 10 0000 0000 0000) is inserted after every data sample

originating from the 2× interpolation filter. A digital multiplexer

switching at a rate of 4 × fDATA between the interpolation filter

output and a data register containing the midscale data sample is

used as shown in Figure 28 to implement this option. Therefore,

the DAC output is now forced to return to its differential midscale

current value (that is, IOUTA − IOUTB at 0 mA) after reconstructing

each data sample from the digital filter.

The net effect is to increase the DAC update rate such that the

zero in the sin(x)/x frequency response occurs at 4 × fDATA

accompanied by a corresponding reduction in output power as

shown in Figure 29. Note that if the high-pass response of the

2× interpolation filter is also selected, this action can be

modeled as a quarter-wave digital mixing process, because this

is equivalent to digitally mixing the impulse response of the

low-pass filter with a square wave having a frequency of exactly

fDATA (that is, fDAC/4).

It is important to realize that the zero-stuffing option by itself

does not change the location of the images, but rather changes

their signal level, amplitude flatness, and relative weighting. For

instance, in the previous example, the pass-band amplitude

flatness of the lower and upper sideband images centered

around fDATA are improved to 0.14 dB and 0.24 dB, respectively,

while the signal level changes to −6.5 dBFS and −7.5 dBFS. The

lower or upper sideband image centered around 3 × fDATA

exhibit an amplitude flatness of 0.77 dB and 1.29 dB with signal

levels of approximately −14.3 dBFS and −19.2 dBFS.

PLL CLOCK MULTIPLIER OPERATION

The phase-lock loop (PLL) clock multiplier circuitry, along with

the clock distribution circuitry, can produce the necessary

internally synchronized 1×, 2×, and 4× clocks for the edge-

triggered latches, 2× interpolation filter, zero-stuffing

multiplier, and DAC. Figure 30 shows a functional block

diagram of the PLL clock multiplier, which consists of a phase

detector, a charge pump, a voltage controlled oscillator (VCO),

a prescaler, and digital control input/output. The clock

distribution circuitry generates all the internal clocks for a given

mode of operation. The charge pump and VCO are powered

from PLLVDD, and the differential clock input buffer, phase

detector, prescaler, and clock distribution circuitry are powered

from CLKVDD. To ensure optimum phase noise performance

from the PLL clock multiplier and clock distribution circuitry,

PLLVDD and CLKVDD must originate from the same clean

analog supply.

CHARGE

PUMP

PHASE

DETECTOR

EXT/INT

CLOCK CONTROL

PRESCALER

CLKVDD

OUT1×

CLKCOM

CLK+

LPF

PLLVDD

DNC

2.7V

3.6V

PLLCOM

CLOCK

DISTRIBUTION

–

PLLLOCK

CLK–

VCO

AD9772A

Figure 30. Clock Multiplier with PLL Clock Multiplier Enabled

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