AD7475ARMZ datasheet(17/24 Pages) AD

17 / 24 page

Data Sheet

AD7475/AD7495

Rev. D | Page 17 of 24

To exit this operating mode and power up the AD7475/AD7495

again, a dummy conversion is performed. On the falling edge of

CS, the device begins to power up and continues to power up as

long as CS is held low until after the falling edge of the 10

th SCLK.

The device is fully powered up once 16 SCLKs have elapsed,

and valid data results from the next conversion, as shown in

Figure 21. If CS is brought high before the second falling edge

of SCLK, the AD7475/AD7495 go back into partial power-down

again. This avoids accidental power-up due to glitches on the CS

line; although the device may begin to power up on the falling

edge of CS, it powers down again on the rising edge of CS. If in

partial power-down and CS is brought high between the second

and tenth falling edges of SCLK, the device enters full power-

down mode.

Power-Up Time

The power-up time of the AD7475/AD7495 from partial power-

down is typically 1 μs, which means that with any frequency of

SCLK up to 20 MHz, one dummy cycle is sufficient to allow the

device to power up from partial power-down. Once the dummy

cycle is complete, the ADC is fully powered up and the input

signal is acquired properly. The quiet time, tQUIET, must still be

allowed from the point where the bus goes back into three-state

after the dummy conversion to the next falling edge of CS. When

running at a 1 MSPS throughput rate, the AD7475/AD7495 power

up and acquire a signal within ±0.5 LSB in one dummy cycle, 1 μs.

When powering up from the power-down mode with a dummy

cycle, as in Figure 21, the track-and-hold that was in hold mode

while the device was powered down returns to track mode after

the first SCLK edge the device receives after the falling edge of

CS. This is shown as Point A in Figure 21. Although at any SCLK

frequency one dummy cycle is sufficient to power up the device

and acquire VIN, it does not necessarily mean that a full dummy

cycle of 16 SCLKs must always elapse to power up the device

and fully acquire VIN; 1 μs is sufficient to power up the device

and acquire the input signal. If, for example, a 5 MHz SCLK

frequency were applied to the ADC, the cycle time would be

3.2 μs. In one dummy cycle, 3.2 μs, the device would be powered up

and VIN fully acquired. However, after 1 μs with a 5 MHz SCLK,

only 5 SCLK cycles would have elapsed. At this stage, the ADC

would be fully powered up and the signal acquired. In this case,

the CS can be brought high after the 10

th SCLK falling edge and

brought low again after a time, tQUIET, to initiate the conversion.

FULL POWER-DOWN MODE

Full power-down mode is intended for use in applications

where slower throughput rates are required than that in the

partial power-down mode, because powering up from a full

power-down would not be complete in just one dummy

conversion. This mode is more suited to applications where a

series of conversions performed at a relatively high throughput

rate are followed by a long period of inactivity and therefore

power down. When the AD7475/AD7495 are in full power-

down, all analog circuitry is powered down.

SCLK

SDATA

INVALID DATA

VALID DATA

THE PART BEGINS

TO POWER UP

THE PART IS FULLY

POWERED UP

Figure 21. Exiting Partial Power-Down Mode

SCLK

SDATA

INVALID DATA

THE PART BEGINS

TO POWER UP

THE PART ENTERS

FULL POWER-DOWN

THE PART ENTERS

PARTIAL POWER-DOWN

THREE-STATE

Figure 22. Entering Full Power-Down Mode

AD7475ARMZ датащи(PDF) 17 Page - Analog Devices

AD7475ARMZ датащи(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL