AD5644R datasheet(24/28 Pages) AD

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AD5624R/AD5644R/AD5664R

Data Sheet

Rev. D | Page 24 of 28

MICROPROCESSOR INTERFACING

AD5624R/AD5644R/AD5664R to Blackfin ADSP-BF53x

Interface

Figure 58 shows a serial interface between the AD5624R/

AD5644R/AD5664R and the Blackfin® ADSP-BF53x micro-

processor. The ADSP-BF53x processor family incorporates two

dual-channel synchronous serial ports, SPORT1 and SPORT0,

for serial and multiprocessor communications. Using SPORT0

to connect to the AD5624R/AD5644R/AD5664R, the setup for

the interface is that the DT0PRI drives the DIN pin of the

AD5624R/AD5644R/AD5664R, while TSCLK0 drives the SCLK

of the part. The SYNC is driven from TFS0.

AD5624R/

AD5644R/

AD5664R1

ADSP-BF53x1

SYNC

TFS0

DIN

DTOPRI

SCLK

TSCLK0

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 58. Blackfin ADSP-BF53x Interface to AD5624R/AD5644R/AD5664R

AD5624R/AD5644R/AD5664R to 68HC11/68L11

Interface

Figure 59 shows a serial interface between the AD5624R/

AD5644R/AD5664R and the 68HC11/68L11 microcontroller.

SCK of the 68HC11/68L11 drives the SCLK of the AD5624R/

AD5644R/AD5664R, while the MOSI output drives the serial

data line of the DAC.

The SYNC signal is derived from a port line (PC7). The setup

conditions for correct operation of this interface are that the

68HC11/68L11 is configured with its CPOL bit as 0 and its

CPHA bit as 1. When data is transmitted to the DAC, the

SYNC line is taken low (PC7). When the 68HC11/68L11 is

configured as described previously, data appearing on the

MOSI output is valid on the falling edge of SCK. Serial data

from the 68HC11/

68L11 is transmitted in 8-bit bytes with only eight falling clock

edges occurring in the transmit cycle. Data is transmitted MSB

first. To load data to the AD5624R/AD5644R/AD5664R, PC7 is

left low after the first eight bits are transferred, and a second

serial write operation is performed to the DAC; PC7 is taken

high at the end of this procedure.

68HC11/68L111

SYNC

PC7

SCLK

SCK

DIN

MOSI

1ADDITIONAL PINS OMITTED FOR CLARITY.

AD5624R/

AD5644R/

AD5664R1

Figure 59. 68HC11/68L11 Interface to AD5624R/AD5644R/AD5664R

AD5624R/AD5644R/AD5664R to 80C51/80L51 Interface

Figure 60 shows a serial interface between the AD5624R/

AD5644R/AD5664R and the 80C51/80L51 microcontroller. The

setup for the interface is that the TxD of the 80C51/80L51 drives

SCLK of the AD5624R/AD5644R/AD5664R, while RxD drives the

serial data line of the part. The SYNC signal is derived from a bit-

programmable pin on the port. In this case, port line P3.3 is used.

When data is transmitted to the AD5624R/AD5644R/AD5664R,

P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes

only; thus, only eight falling clock edges occur in the transmit cycle.

To load data to the DAC, P3.3 is left low after the first eight bits are

transmitted, and a second write cycle is initiated to transmit the

second byte of data. P3.3 is taken high following the completion of

this cycle. The 80C51/80L51 outputs the serial data in LSB first

format. The AD5624R/AD5644R/AD5664R must receive data with

the MSB first. The 80C51/80L51 transmit routine should take this

into account.

80C51/80L511

SYNC

P3.3

SCLK

TxD

DIN

RxD

1ADDITIONAL PINS OMITTED FOR CLARITY.

AD5624R/

AD5644R/

AD5664R1

Figure 60. 80C51/80L51 Interface to AD5624R/AD5644R/AD5664R

AD5624R/AD5644R/AD5664R to MICROWIRE Interface

Figure 61 shows an interface between the AD5624R/AD5644R/

AD5664R and any MICROWIRE-compatible device. Serial

data is shifted out on the falling edge of the serial clock and is

clocked into the AD5624R/AD5644R/AD5664R on the rising

edge of the SK.

MICROWIRE1

SYNC

SCLK

DIN

1ADDITIONAL PINS OMITTED FOR CLARITY.

AD5624R/

AD5644R/

AD5664R1

Figure 61. MICROWIRE Interface to AD5624R/AD5644R/AD5664R

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