LTC3312SAAVPBF datasheet(14/28 Pages) AD

14 / 28 page

LTC3312SA

Rev. 0

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PVIN1 and PVIN2 are not connected internally and should

be externally shorted to a single input supply. Each PVIN

pin should have its own input bypass capacitor to PGND.

Mode Selection

The buck switching regulators operate in three different

modes set by the MODE/SYNC pin: pulse-skipping mode

(when the MODE/SYNC pin is set low), forced continu-

ous mode (when the MODE/SYNC pin is floating), and

Burst Mode (when the MODE/SYNC pin is set high). The

MODE/SYNC pin sets the operating mode for both buck

switching regulators.

In pulse-skipping mode, the oscillator operates continu-

ously, and positive SW transitions are aligned to the clock.

Negative inductor current is disallowed, and switch pulses

are skipped for light loads to regulate the output voltage.

In forced continuous mode, the oscillator operates con-

tinuously. The top switch turns on every cycle and regu-

lation is maintained by allowing the inductor current to

reverse at light load. This mode allows the buck to run

at a fixed frequency with minimal output ripple. In forced

continuous mode, if the inductor current reaches 4A (typi-

cal) into the SW pin, the bottom switch will turn off for

the remainder of the cycle to limit the current.

In Burst Mode operation at light loads, the output capaci-

tor is charged to a voltage slightly higher than its regu-

lation point. The regulator then goes into a sleep state,

during which time the output capacitor provides the

load current. In sleep, most of the regulator’s circuitry is

powered down, helping conserve input power. When the

output voltage drops below its programmed value, the

circuitry is powered on and another burst cycle begins.

The sleep time decreases as load current increases. In

Burst Mode operation, the regulator will burst at light

loads whereas at higher loads it will operate in constant

frequency PWM mode.

Synchronizing the Oscillator to an External Clock

The LTC3312SA’s internal oscillator is synchronized

through an internal PLL circuit to an external frequency

by applying a square wave clock signal to the MODE/

SYNC pin. During synchronization, the Buck 1 top power

switch turn-on is locked to the rising edge of the external

frequency source. The Buck 2 top switch turn-on will be

180 degrees out of phase with respect to Buck 1. While

synchronizing, the buck switching regulators operate

in forced continuous mode. The slope compensation is

automatically adapted to the external clock frequency. The

synchronization frequency range is 1MHz to 3MHz.

After detecting an external clock on the first rising edge

of the MODE/SYNC pin, the internal PLL gradually adjusts

its operating frequency to match the frequency and phase

of the signal on the MODE/SYNC pin. When the external

clock is removed, the LTC3312SA will detect the absence

of the external clock within approximately 10μs. During

this time, the PLL will continue to provide clock cycles.

Once the external clock removal has been detected, the

oscillator will gradually adjust its operating frequency to

the one programmed by the RT pin.

Output Power Good

Both buck switching regulators have an external open-

drain PGOOD pin, that operates independently of the

other. When a buck output voltage is within the –2/+10%

(typical) window of the nominal regulation voltage, the

output is considered good. The corresponding open-drain

PGOOD pin goes high impedance and is typically pulled

high with an external resistor. Otherwise, an internal pull-

down device will pull the corresponding PGOOD pin low.

Each PGOOD pin is also pulled low during the following

fault conditions: the corresponding buck EN pin is low, VIN

is too low, or thermal shutdown. To filter noise and short

duration output voltage transients, the lower thresholds

have a hysteresis of 1.1% (typical), the upper thresholds

have a hysteresis of 2.2% (typical), and transitions of the

PGOOD pins have a built-in time delay, typically 100µs.

Output Overvoltage Protection

If there is an output overvoltage event, which occurs when

the FB pin voltage is greater than 110% of nominal, the

buck regulator top power switch will be turned off. If the

output remains out of regulation for more than 100µs, the

PGOOD pin will be pulled low.

OPERATION

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