Device description

L99UDL01

10/24

DB3264 Rev 3

2

Device description

2.1

Overview

The L99UDL01 is a 6+2 channel half bridge driver monolithic integrated circuit designed to

power a centralized door lock system. This device is made possible by the incorporation of

current regulated drivers limiting the current in the door lock motors to a preset level (for

example the current levels seen at a 9 V battery).

The current is regulated by PWMming the door lock actuators at a programmed frequency

and duty cycle.

2.2

Supply monitoring

2.2.1

The Vs supply has a low voltage warning function with hysteresis. When Vs drops below

use. Actuation can be restarted via SPI frame or EN_OUT rising edge according to

cleared only upon read & clear.

2.2.2

be restarted according to configuration registers via SPI frame or EN_OUT rising edge or by

setting the EN_ON bit. The VSOVSD bit (diagnostic register 02H) remains set until read &

clear SPI frame.

2.2.3

VDD Monitoring

The VDD pin (5V/3.3V) is a supply pin for the L99UDL01 I/O. This pin is monitored by 2

under voltage conditions. In case of an undervoltage condition during operational mode

(VDD < VDDUV) the device will enter into stand-by mode and all of the control registers will

be reset to their default values after tVDDUV. In case of an undervoltage condition

(VDD<VDDSLEEP), the device enters into the ultra-low quiescent sleep mode and the

internal regulator is disabled.

Standby mode until a CSN wake-up has occurred. The reset (RSTB) bit will remain set until

the first SPI communication.

2.2.4

3V3 Monitoring

The internal 3.3 V regulator, 3V3, is monitored for under voltage conditions to ensure the

logic integrity. The 3V3 supply has a low voltage warning function with hysteresis. When the