ESR =

∆ VESR

IOUT + ( ∆ IP−P

IOUT × D(1 − D)

∆ VQ × × fSW

where:

(VIN − VOUT) × VOUT

VIN × fSW × L

and:

D =

VOUT

VIN

at lower input voltages to avoid possible undershoot below the UVLO threshold during transient loading.

Inductor Selection

See Table 1 for inductor selection. The nominal standard value selected should be within ±50% of the specified

inductance. The specified values applies to all output voltage settings.

Table 1. Inductor Selection

PART

INDUCTANCE (µH)

2.2

10

Output Capacitor

For optimal phase margin (> 60 degrees, typ), the recommended output capacitances are shown in Table 2.

Recommended values are the actual capacitances after voltage derating is taken into account.

If a lower output capacitance is required, contact the factory for recommendations. Additional output capacitance may

be needed based on application-specific output-voltage-ripple requirements. The specified values applies to all output

voltage settings.

Table 2. Output-Capacitance Selection

PART

OUTPUT CAPACITANCE (µF)

30

44

The allowable output-voltage ripple and the maximum deviation of the output voltage during step-load currents determine

(caused by the ESR of the output capacitor). Use low-ESR ceramic or aluminum electrolytic capacitors at the output.

ESR requirement and choose the capacitor accordingly. If using ceramic capacitors, assume the contribution to the

output ripple voltage from the ESR and the capacitor discharge to be equal. The following equations show the output

capacitance and ESR requirement for a specified output-voltage ripple.

Equation 2:

ESR =

∆ VESR

∆ IP−P

MAX25232

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