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STM32L100RC датащи(PDF) 76 Page - STMicroelectronics

номер детали STM32L100RC
подробное описание детали  Ultra-low-power 32b MCU ARM®-based Cortex®-M3, 256KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC, memory I/F
PDF  106 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STM32L100RC датащи(HTML) 76 Page - STMicroelectronics

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Electrical characteristics
STM32L100RC
76/106
DocID024995 Rev 5
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 14 and
Table 43, respectively.
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under the conditions summarized in Table 12.
Table 43. I/O AC characteristics(1)
OSPEEDRx
[1:0] bit
value(1)
Symbol
Parameter
Conditions
Min
Max(2) Unit
00
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
400
kHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
400
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
625
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
625
01
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
2
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
1
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
125
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
250
10
Fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
10
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
2
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
25
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
125
11
Fmax(IO)out Maximum frequency(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
50
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
8
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
30
-tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
-8
-
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx
reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. The maximum frequency is defined in Figure 14.



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