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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPC58EEX датащи(PDF) 115 Page - STMicroelectronics |
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SPC58EEX датащи(HTML) 115 Page - STMicroelectronics |
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115 / 154 page  DS11646 Rev 4 115/154 SPC58EEx, SPC58NEx Electrical characteristics 128 Figure 37. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 1 3.18.3 Ethernet timing The Ethernet provides both MII and RMII interfaces. The MII and RMII signals can be configured for either CMOS or TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. Please check the device pinout details to review the packages supporting MII and RMII. 3.18.3.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK) The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency. Note: In the following table, all timing specifications are referenced from RX_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V. Last Data Last Data SIN SOUT SS First Data First Data Data Data SCK Input SCK Input (CPOL = 0) (CPOL = 1) tA tDIS tSUI tHI tSUO tHO Table 61. MII receive signal timing Symbol C Characteristic Value Unit Min Max M1 CC D RXD[3:0], RX_DV, RX_ER to RX_CLK setup 5 — ns M2 CC D RX_CLK to RXD[3:0], RX_DV, RX_ER hold 5 — ns M3 CC D RX_CLK pulse width high 35% 65% RX_CLK period M4 CC D RX_CLK pulse width low 35% 65% RX_CLK period |
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