SPC572L60F2 datasheet(22/112 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC572Lx

22/112

DocID027866 Rev 5

3.7

DC electrical specifications

The following table describes the DC electrical specifications.

VIN

SR C I/O input voltage

range

—0

—

5.5

Injection current

IIC

T DC injection current

(per pin)(13),(14),(15)

Digital pins and

analog pins

–3.0

—

3.0

IMAXSEG

SR D Maximum current per

power segment(16)

—–80

—

1. The ranges in this table are design targets and actual data may vary in the given range.

2. Maximum operating frequency is applicable to the core and platform for the device. See the Clocking chapter in the

SPC572Lx Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the

device.

3. Core voltage as measured on device pin to guarantee published silicon performance.

4. During power ramp, voltage measured on silicon might be lower. Maximum performance is not guaranteed, but correct

silicon operation is guaranteed. Refer to the Power Management and Reset Generation Module chapters in the SPC572Lx

Microcontroller Reference Manual for further information.

5. The VDD_HV_PMC supply providing power to the internal regulator is shorted with the VDD_HV_IO supply within package.

6. LVD400 can be disabled by SW (always enabled after power-up).

7. Maximum voltage is not permitted for entire product life. See Absolute maximum rating.

8. When internal LVD/HVDs are disabled, external monitoring is required to guarantee correct device operation.

9. Reduced output/input capabilities below 4.2 V. See performance operating values in I/O pad electrical characteristics. Not

all functionality are guaranteed below 4.2 V. Please check specific supply constraints by module in Table 9 (Device

operating conditions).

10. VDD_HV_IO_JTAG supply is shorted with VDD_HV_OSC supply within package.

11. Flash read, program, and erase operations are supported for a minimum VDD_HV_FLA value of 3.0 V.

12. This voltage can be measured on the pin but is not supplied by an external regulator. The Power Management Controller

generates PORs based on this voltage.

13. Full device lifetime without performance degradation

14. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See the

Absolute maximum ratings table for maximum input current for reliability requirements.

15. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is

above the supply rail, current is injected through the clamp diode to the supply rail. For external RC network calculation,

assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.

16. Sum of all controller pins (including both digital and analog) must not exceed 150 mA. A VDD_HV_IO power segment is

defined as one or more GPIO pins located between two VDD_HV_IO supply pins.

Table 9. Device operating conditions(1) (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

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