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SPC584CX датащи(PDF) 42 Page - STMicroelectronics

номер детали SPC584CX
подробное описание детали  SPC58 C Line - 32 bit Power Architecture automotive MCU Dual z4 cores 180 MHz, 4 MBytes Flash, HSM, ASIL-B
PDF  153 Pages
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Electrical characteristics
SPC584Cx, SPC58ECx
42/153
DS11620 Rev 8
4.10.2
PLL1
PLL1 is a frequency modulated PLL with Spread Spectrum Clock Generation (SSCG)
support.
Table 21. PLL1 electrical characteristics
Symbol
C
Parameter
Conditions
Value
Unit
Min
Typ
Max
fPLL1IN
SR
—
PLL1 input clock(1)
—
37.5
—
87.5
MHz
ΔPLL1IN
SR
—
PLL1 input clock duty
cycle(1)
—35
—
65
%
fINFIN
SR
—
PLL1 PFD (Phase
Frequency Detector)
input clock frequency
—
37.5
87.5
MHz
fPLL1VCO
CC
P
PLL1 VCO frequency
—
600
—
1400
MHz
fPLL1PHI0
CC
D
PLL1 output clock PHI0
—
4.762
—
FSYS(2)
MHz
tPLL1LOCK
CC
P
PLL1 lock time
—
—
—
50
µs
fPLL1MOD
CC
T
PLL1 modulation
frequency
—
—
—
250
kHz
|δPLL1MOD|CC
T
PLL1 modulation depth
(when enabled)
Center spread(3)
0.25
—
2
%
Down spread
0.5
—
4
%
|ΔPLL1PHI0SPJ|
(4)
CC
T
PLL1_PHI0 single period
peak to peak jitter
fPLL1PHI0 =
200 MHz, 6-sigma
——
500(5)
ps
IPLL1
CC
D
PLL1 consumption
FINE LOCK state
—
—
5
mA
1. PLL1IN clock retrieved directly from either internal PLL0 or external FXOSC clock. Input characteristics are granted when
using internal PPL0 or external oscillator is used in functional mode.
2. Refer to Section 4.3: Operating conditions for the maximum operating frequency.
3. The device maximum operating frequency FSYS (max) includes the frequency modulation. If center modulation is selected,
the FSYS must be below the maximum by MD (Modulation Depth Percentage), such that FSYS(max)=FSYS(1+MD%).
Refer to the Reference Manual for the PLL programming details.
4. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to
the output CLKOUT pin.
5. 1.25 V±5%, application noise below 40 kHz at VDD_LV pin - no frequency modulation.



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