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WF200D датащи(PDF) 21 Page - Silicon Laboratories

номер детали WF200D
подробное описание детали  WF200 Data Sheet: Wi-Fi짰 Network Co-Processor
PDF  38 Pages
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производитель  SILABS [Silicon Laboratories]
домашняя страница  http://www.silabs.com
Logo SILABS - Silicon Laboratories

WF200D датащи(HTML) 21 Page - Silicon Laboratories

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4.8.2 SDIO Specification
Figure 4.2. SDIO Interface Timing Parameters
Table 4.13. SDIO Interface Timing Specifications
Symbol
Description
Min
Typ
Max
Unit
Conditions
tCLK_HS
Clock period in high speed
mode
19.23
ns
CL ≤ 20pF
tCLK_DS
Clock period in default speed
mode
38.46
ns
CL ≤ 20pF
tCLK_LO
Clock low time
9
ns
CL≤ 20pF
tCLK_HI
Clock high time
9
ns
CL≤ 20pF
CMD, DAT0~3 Inputs (with reference to SDIO_CLK)
tSU
Input Set time
3
ns
CL≤ 20pF
tHD
Input Hold time
3
ns
CL≤ 20pF
CMD, DAT0~3 Outputs (with reference to SDIO_CLK)
tODLY_CLKr,
tODLY_CLKf
Output delay time (relative to
rising and falling edge) for VDD
= 3.3V
11
ns
VDDIO = 3.3V;
CL≤ 20pF
Output delay time (relative to
rising and falling edge) for VDD
= 1.8V
22
ns
VDDIO = 1.8V;
CL≤ 20pF
tOH
Output Hold time
3
ns
CL≤ 20pF
1. Output data can be latched either on rising edge (HS mode) or falling edge (DS mode) of CLK
2. All timing parameters valid for output load of up to 2 mA
WF200 Data Sheet: Wi-Fi® Network Co-Processor
Electrical Specifications
silabs.com | Building a more connected world.
Rev. 1.1 | 21



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