STM32WB55CC_V02 datasheet(21/193 Pages) STMICROELECTRONICS

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DS11929 Rev 11

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STM32WB55xx STM32WB35xx

Functional overview

3.3.4

Embedded SRAM

The STM32WB55xx devices feature up to 256 Kbytes of embedded SRAM, split in three

blocks:



SRAM1: up to 192 Kbytes mapped at address 0x2000 0000



SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000,

with hardware parity check (this SRAM can be retained in Standby mode)



SRAM2b: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and

mirrored at 0x1000 8000 with hardware parity check

The STM32WB35xx devices feature 96 Kbytes of embedded SRAM, split in three blocks:



SRAM1: 32 Kbytes mapped at address 0x2000 0000



SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000,

with hardware parity check (this SRAM can be retained in Standby mode)



SRAM2b: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and

mirrored at 0x1000 8000 with hardware parity check

SRAM2a and SRAM2b can be write-protected, with 1-Kbyte granularity. A section of the

SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the

host CPU1.

The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock

speeds.

3.4

Security and safety

The STM32WB55xx and STM32WB35xx contain many security blocks both for the BLE or

IEEE 802.15.4 and the Host application.

It includes:



Customer storage of the BLE and 802.15.4 keys



Secure Flash memory partition for RF subsystem-only access



Secure SRAM partition, that can be accessed only by the RF subsystem



True random number generator (RNG)



Advance encryption standard hardware accelerators (AES-128bit and AES-256bit,

supporting chaining modes ECB, CBC, CTR, GCM, GMAC, CCM)



Private key acceleration (PKA) including:

–

Modular arithmetic including exponentiation with maximum modulo size of 3136

bits

–

Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA

verification with maximum modulo size of 521 bits



Cyclic redundancy check calculation unit (CRC)

A specific mechanism is in place to ensure that all the code executed by the RF subsystem

CPU2 can be secure, whatever the Host application. For the AES1 a customer key can be

managed by the CPU2 and used by the CPU1 to encrypt/decrypt data.

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