21

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

1

0

0

1

1

1

0

FINT3

FINT2

FINT1

FINT0

FIFST1

FIFST0

FILLEN

FIFEN

The Data FIFO Configuration Register configures:

•

FIFO fill interrupt condition

•

FIFO fill start condition

•

FIFO fill on synchronous pattern

•

FIFO Enable

Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that

identifies the bits to be written to the Data FIFO Configuration Register.

Bit [7..4] – FIFO Fill Bit Count: This sets the number of bits that are received before generating an

external interrupt to the host processor that the receive FIFO data is ready to be read out. It is

possible to set the maximum fill level to 15 (16-bits), but the designer must account for the

processing time it will take to read out the data before a register overrun occurs, at which data

will be lost. It is recommended to set the fill value to half of the desired number of bits to be read

to ensure enough time for additional processing. See Status Register for description of FIFO

status bits that may be read and FIFO Read Register for polling and interrupt-driven FIFO reads

from the SPI bus.

Bit [3..2] – FIFO Fill Start Condition: These bits set the condition at which the FIFO begins filling with

data. Table 10 describes the start conditions. See Valid Data configuration in Receiver Control

Register

.

Table 10.

Bit [1] – Synchronous Pattern FIFO Fill Enable: When set, the FIFO will begin filling with data when it

detects the FIFO Fill Start Condition as defined in bits[3..2] above. The FIFO fill stops and the

FIFO is reset when this bit is cleared. To restart simply clear the bit and set again.

Bit [0] – FIFO Enable: This bit enables the internal data FIFO when set. The FIFO is used to store data

during receive. If the FIFO is enabled by setting this bit, pin 6 becomes nFSEL and pin 7 becomes

FINT. See Data Buffer Setup Register section for details on the FIFO configuration.

Fill Start Condition

FIFST1 FIFST0

Valid Data

0

0

Synch Word

0

1

Valid Data and Sync Word

1

0

Continuous Fill

1

1