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PCF8545ATT датащи(PDF) 8 Page - NXP Semiconductors |
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PCF8545ATT датащи(HTML) 8 Page - NXP Semiconductors |
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8 / 54 page ![]() PCA8576F All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 3 December 2014 8 of 54 NXP Semiconductors PCA8576F Automotive 40 × 4 LCD driver Remark: A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. 7.2.3 Timing and frame frequency The PCA8576F timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the correct timing relationship between each PCA8576F in the system is maintained by the synchronization signal at pin SYNC. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency is a fixed division of the clock frequency from either the internal or an external clock: . 7.2.4 Blinking The display blinking capabilities of the PCA8576F are very versatile. The whole display can blink at frequencies selected by the blink-select command (see Table 11). The blink frequencies are derived from the clock frequency. The ratio between the clock and blink frequencies depends on the blink mode selected (see Table 11). An additional feature is for an arbitrary selection of LCD segments/elements to blink. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blink frequency. This mode can also be specified by the blink-select command. In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of LCD segments/elements can blink by selectively changing the display RAM data at fixed time intervals. The entire display can blink at a frequency other than the nominal blink frequency. This can be effectively performed by resetting and setting the display enable bit E at the required rate using the mode-set command (see Table 7). [1] Blink modes 1, 2 and 3 and the nominal blink frequencies correspond to an oscillator frequency (fclk) of 4800 Hz (see Section 13). f fr f clk 24 ------- = Table 12. Blinking frequencies Blink mode Normal operating mode ratio Nominal blink frequency[1] Unit off - blinking off Hz 16.2 Hz 23.1 Hz 31.6 Hz f clk 768 ---------- f clk 1536 ------------- f clk 3072 ------------- |
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