5

PS8820

02/28/06

PI6C21200

1:12 Clock Driver for Intel

PCI-Express Chipsets

Data Byte 0: Control Register

Bit

Descriptions

Type

Power Up Condition

Output(s) Affected

0

FSB Gear Ratio SMBus

RW

1

1

FSB Gear Ratio SMBus

RW

2

FSB Gear Ratio SMBus

RW

0

3

FSB Gear Ratio SMBus

RW

4

FS_A PI6C410B latched input

RW

Latch

5

Reserved

RW

1

6

Group of 2 gear ratio select

1 = 1:1, 0 = Gear Raito

RW

1

OUT[10:11],

OUT[10:11]#

7

Group of 10 gear ratio select

1 = 1:1, 0 = Gear Raito

RW

1

OUT[0:9],

OUT[0:9]#

Data Byte 1: Control Register

Bit

Descriptions

Type

Power Up Condition

Output(s) Affected

0

OUTPUTS enable

1 = Enabled

0 = Hi-Z

RW

1 = Enabled

OUT0, OUT0#

1

RW

1 = Enabled

OUT1, OUT1#

2

RW

1 = Enabled

OUT2, OUT2#

3

RW

1 = Enabled

OUT3, OUT3#

4

RW

1 = Enabled

OUT4, OUT4#

5

RW

1 = Enabled

OUT5, OUT5#

6

RW

1 = Enabled

OUT6, OUT6#

7

RW

1 = Enabled

OUT7, OUT7#

Data Byte 2: Control Register

Bit

Descriptions

Type

Power Up Condition

Output(s) Affected

0

OUTPUTS enable

1 = Enabled

0 = Hi-Z

RW

1 = Enabled

OUT8, OUT8#

1

RW

1 = Enabled

OUT9, OUT9#

2

RW

1 = Enabled

OUT10, OUT10#

3

RW

1 = Enabled

OUT11, OUT11#

4

Reserved

RW

5

PLL/BYPASS#

0 = Fanout,1 = PLL

RW

1 = PLL

OUT[0:11], OUT[0:11]#

6

PLL Bandwidth

0 = High Bandwidth,

1 = Low Bandwidth

RW

1 = Low

OUT[0:11], OUT[0:11]#

7

Outputs current select at PWRDWN = 1

0 = HiZ

RW

1

Note:

1. When FS_A = 1, Bit 1 = 0 and Bit 3 = 1; When FS_A = 0, Bit 1 = 1 and Bit 3 = 0