PI6C410B

Clock Generator for Intel PCI-Express Server Chipset

13

PS8811A

02/01/06

Symbol

Outputs

Parameters

Min

Max.

Units

Notes

CPU, SRC

Rise and Fall Time

(measured between 0.175V to 0.525V)

175

700

ps

3, 4

PCI/PCIF, REF

Rise/Fall Edge Rate

(measured between 0.8V to 2.0V)

1.0

4.0

V/ns

6

USB

Rise/Fall Edge Rate

(measured between 0.8V to 2.0V)

1.0

2.0

6

CPU, SRC

Rise and Fall Time Variation

125

ps

3, 4

CPU

CPU – CPU Skew

100

ps

3, 5

SRC

SRC – SRC Skew

250

3, 5

PCI/PCIF, REF

PCI – PCI Skew / REF - REF Skew (mea-

sured at 1.5V)

500

6

CPU

Cycle – Cycle Jitter

85

3, 5

SRC

Cycle – Cycle Jitter

125

3, 5

PCI/PCIF

Cycle – Cycle Jitter (measured at 1.5V)

500

6

USB

Cycle – Cycle Jitter (measured at 1.5V)

350

6

REF

Cycle – Cycle Jitter (measured at 1.5V)

1000

6

CPU, SRC

Voltage High including overshoot

660

1150

mV

3, 4

CPU, SRC

Voltage Low including undershoot

-300

3, 4

CPU, SRC

Absolute crossing point voltages

250

550

3, 4

CPU, SRC

Total Variation of Vcross over all edges

140

3, 4

CPU, SRC

Duty Cycle

45

55

%

3, 5

REF, USB,

PCI/PCIF

Duty Cycle (measured at 1.5V)

45

55

6

All clock stabilization from power-up

<1.8

ms

Fig 2

Pwrdwn

Differential output enable after PwrDwn

de-assertion

300

μs

Fig 2

Pwrdwn

PwrDwn rise and fall time

5.0

ns

Notes:

3. Test configuration is Rs = 33.2Ω, Rp = 49.9Ω, and 2pF.

4. Measurement taken from Single Ended waveform.

5. Measurement taken from Differential waveform.

6. Two Loads for PCI/PCIF and USB. Three loads for REF. RS=12Ω5%, Max 20" into 5pF load with 60Ω impedance.