AS1130 datasheet(18/66 Pages) AMSCO

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AS1130 − Detailed Description

• Acknowledge: Each receiving device, when addressed, is

obliged to generate an acknowledge after the reception

of each byte. The master device must generate an extra

clock pulse that is associated with this acknowledge bit.

A device that acknowledges must pull down the SDA line

during the acknowledge clock pulse in such a way that the

SDA line is stable LOW during the HIGH period of the

acknowledge clock pulse. Of course, setup and hold times

must be taken into account. A master must signal an end

of data to the slave by not generating an acknowledge bit

on the last byte that has been clocked out of the slave. In

this case, the slave must leave the data line HIGH to enable

the master to generate the STOP condition.

• Figure 24 details how data transfer is accomplished on the

I²C bus. Depending upon the state of the R/W bit, two

types of data transfer are possible:

• Master Transmitter to Slave Receiver. The first byte

transmitted by the master is the slave address,

followed by a number of data bytes. The slave returns

an acknowledge bit after the slave address and each

received byte.

• Slave Transmitter to Master Receiver. The first byte,

the slave address, is transmitted by the master. The

slave then returns an acknowledge bit. Next, a

number of data bytes are transmitted by the slave to

the master. The master returns an acknowledge bit

after all received bytes other than the last byte. At the

end of the last received byte, a not-acknowledge is

returned. The master device generates all of the serial

clock pulses and the START and STOP conditions. A

transfer is ended with a STOP condition or a repeated

START condition. Since a repeated START condition is

also the beginning of the next serial transfer, the bus

will not be released.

The AS1130 can operate in the following slave modes:

• Slave Receiver Mode. Serial data and clock are received

through SDA and SCL. After each byte is received, an

acknowledge bit is transmitted. START and STOP

conditions are recognized as the beginning and end of a

serial transfer. Address recognition is performed by

hardware after reception of the slave address and

direction bit.

• Slave Transmitter Mode. The first byte (the slave

address) is received and handled as in the slave receiver

mode. However, in this mode the direction bit will indicate

that the transfer direction is reversed. Serial data is

transmitted on SDA by the AS1130 while the serial clock

is input on SCL. START and STOP conditions are recognized

as the beginning and end of a serial transfer.

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