AD7380 datasheet(21/31 Pages) AD

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Data Sheet

AD7380-4

Rev. 0 | Page 21 of 31

INTERFACE

The interface to the AD7380-4 is via a serial interface. The

interface consists of CS, SCLK, SDOA, SDOB, SDOC, and

SDOD, and SDI. When referencing a single function of a

multifunction pin, only the portion of the pin name that is relevant

to the specification is listed, such as SDOD. For full pin names of

multifunction pins, refer to the Pin Configuration and Function

Descriptions section.

The CS signal frames a serial data transfer and initiates an ADC

conversion process. The falling edge of CS puts the track-and-

hold into hold mode, at which point the analog input is

sampled and the bus is taken out of three-state. The ADC

conversion operation is driven internally by an on-board

oscillator and is independent of the SCLK signal.

The SCLK signal synchronizes data in and out of the device via

the SDOA, SDOB, SDOC, SDOD, and SDI signals. A minimum

of 16 SCLK cycles are required for a write to or read from a

read is dependent on the resolution of the device and the

configuration settings (see Table 13).

The AD7380-4 has four serial output signals: SDOA, SDOB,

SDOC, and SDOD. Programming the SDO bits in the

CONFIGURATION2 register configures 2-wire, 1-wire, or

4-wire mode. To achieve the highest throughput of the device,

it is required to use either the 2-wire or 4-wire mode to read the

conversion results. If a reduced throughput is required or

oversampling is used, it is possible to use 1-wire mode, SDOA

signal only, for reading conversion results.

Configuring cyclic redundancy check (CRC) operation for SPI

reads, SPI writes and oversampling mode with resolution boost

mode enabled can alter the operation of the interface. Refer to

the CRC section to ensure correct operation.

READING CONVERSION RESULTS

The CS signal initiates the conversion process. A high to low

transition on the CS signal initiates a simultaneous conversion

of the four ADCs, ADC A, ADC B, ADC C, and ADC D. The

AD7380-4 has a one cycle readback latency. Therefore, the

conversion results are available on the next SPI access. Then,

take the CS signal low, and the conversion result clocks out on

the serial data output pins. The next conversion is also initiated

at this point.

The conversion result is shifted out of the device as a 16-bit

result for the AD7380-4. The MSB of the conversion result is

shifted out on the CS falling edge. The remaining data is shifted

out of the device under the control of the serial clock (SCLK)

input. The data is shifted out on the rising edge of SCLK, and

the data bits are valid on both the falling edge and the rising

edge. After the final SCLK falling edge, take CS high again to

return the serial data output pins to a high impedance state.

The number of SCLK cycles to propagate the conversion results

on the serial data output pins is dependent on the serial mode

of operation configured and if resolution boost mode is enabled

(see Figure 36 and Table 13 for details). If CRC reading is

enabled, additional SCLK pulses are required to propagate the

CRC information. See the CRC section for more details.

Because the CS signal initiates a conversion as well as framing

the data any data access must be completed within a single frame.

Table 13. Number of SCLK Cycles (n) Required for Reading

Conversion Results

Interface

Configuration

Resolution

Boost Mode

CRC Read

No. of SCLK

Cycles

4-Wire

Disabled

Enabled

Disabled

Enabled

2-Wire

Disabled

Enabled

Disabled

Enabled

1-Wire

Disabled

Enabled

Disabled

Enabled

n – 2

n – 1

SCLK

CONVERSION RESULTS

SDOx

1CONSULT TABLE 12 FOR VALUES FOR n, THE NUMBER OF SCLK PULSES REQUIRED.

Figure 36. Reading Conversion Results

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