LTC7067

7

Rev. 0

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to bias all the internal circuitry. A bypass capacitor with a

minimum value of 0.1μF should be tied between this pin

and the SGND pin.

driver is biased between this pin and G2RTN pin. An exter-

nal capacitor should be tied between this pin and G2RTN

and placed close to the IC.

G2RTN: G2 MOSFET Driver Return. The G2 gate driver is

to the G2 MOSFET source pin for high noise immunity.

The voltage difference between the G2RTN pin and the

SGND can be −10V to 150V.

G2: G2 MOSFET Gate Driver Output. This pin drives the

gate of the N-channel MOSFET between G2RTN and

driver is biased between this pin and the G1RTN pin. An

external capacitor should be tied between this pin and the

G1RTN pin and placed close to the IC.

G1RTN: G1 MOSFET Driver Return. The G1 gate driver is

to the G1 MOSFET source pin for high noise immunity.

The voltage difference between the G1RTN pin and SGND

can be −10V to 150V.

G1: G1 MOSFET Gate Driver Output. This pin drives

the gate of the N-channel MOSFET between G1RTN

G1IN: Logic input for G1-side driver. If G1IN is unbiased

or floating, G1 is held low.

G2IN: Logic input for G2-side driver. If G2IN is unbiased

or floating, G2 is held low.

FLT: Open Drain Fault Output pin referred to the SGND pin.

OVLO and floating supplies UVLO condition. The typical

pull-down resistor is 60Ω.

SGND: Chip Ground. The exposed pad must be soldered

to the PCB ground for electrical contact and for rated

thermal performance.

PIN FUNCTIONS