SSD1730
Rev 2.0
04/2002
SOLOMON
7
Pin Name
Type
Pin#
Description
Pins for VDD_ROW voltage generator
C8N
I/O
2
The negative-side connection terminal for a
capacitor C11 to generate VDD_ROW output
voltage. (Refer to the application circuit)
VDD_ROW
O
3
This is VDD_ROW output voltage which is the
power supply to the logic circuit part of row driver.
Pins for +V1 voltage generator
AB
O
47
This is the clock output for the external n-channel
MOS transistor control in the +V1 voltage
generator circuit.
XBB
O
48
This is the clock output for the external p-channel
MOS transistor control in the +V1 voltage
generator circuit.
C7N
I/O
4
The negative-side connection terminal for a
capacitor C18 to generate +V1 output voltage.
(Refer to the application circuit)
Pins for row driver voltage conversion circuit
C1PB
I/O
16
The positive-side connection terminal for a
capacitor C10 and C11 to generate -V3B output
voltage. (Refer to the application circuit)
C1NB
I/O
14
The negative-side connection terminal for a
capacitor C10 to generate -V3B output voltage.
(Refer to the application circuit)
-V3B
O
13
This is -V3B output voltage equipped as the middle
voltage level for generating VEE output voltage.
HC
I
10
This pin is used to select 5X or 6X step-up mode.
When it is tied to VSS, 5X step-up mode will be
set. When it is tied to -V3B, 6X step-up mode will
be set.
C5P
I/O
12
The positive-side connection terminal for a
capacitor C8 and C9 to generate VEM output
voltage. (Refer to the application circuit)
C5N
I/O
9
The negative-side connection terminal for a
capacitor C8 to generate VEM output voltage.
(Refer to the application circuit)
VEM
O
8
This is VEM output voltage equipped as the middle
voltage level for generating VEE output voltage.
C6N
I/O
7
The negative-side connection terminal for a
capacitor C9 to generate VEE output voltage.
(Refer to the application circuit)
VEE
O
6
This is VEE output voltage.
Table 8 - Pins for row (common) driver voltage generator
Pin Name
Type
Pin#
Description
XTST
I
46
This is a test pin. This pin must be tied to the
VDD_PWR level in normal application.
NC,1 NC2,
NC3, NC4
NC
11, 25, 26, 34
Dummy Pins. These pins must be left open &
unconnected in normal application.
Table 9 - Test circuit pins and Dummy pins
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