2048-bits Serial Electrically Erasable PROM

AM93LC56

Anachip Corp.

www.anachip.com.tw

Rev. A1 Oct 20, 2003

6/10

ATC

Timing Diagram (1)

FIGURE 2. SYNCHRONOUS DATA TIMING

T

t

SKH

t

SKL

t

CSH

t

CSS

CS

SK

DI

DO(READ)

DO(WRITE)

(WRALL)

(ERASE)

(ERALL)

t

SV

STATUS VALID

t

DF

t

DF

t

PD1

t

PDO

t

DIS

t

DIH

FIGURE 3. DATA READ CYCLE TIMING

CS

SK

+

AO

AN

0

1

1

DI

DN

DO

O

DO

TRI-STATE

+For all instructions, SK cycles before start bit don't care.

*Address Pointer Cycle to the Next Register.

*

t

CS