DLPC4430ZPC datasheet(26/49 Pages) TI

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7 Detailed Description

7.1 Overview

As with prior DLP® electronics solutions, image data is 100% digital from the DLPC4430 input port to the image

projected on to the display screen. The image stays in digital form and is never converted into an analog signal.

The DLPC4430 processes the digital input image and converts the data into bit-plane format as needed by the

DMD. The DLPC4430 display controller is optimized for high-resolution and high-brightness display applications.

Applications include Home Theatre, Smart Display, Digital Signage, and Laser TV.

7.2 Functional Block Diagram

Figure 7-1. Functional Block Diagram

7.3 Feature Description

7.3.1 System Reset Operation

7.3.1.1 Power-up Reset Operation

Immediately following a power-up event, DLPC4430 hardware automatically brings up the Primary PLL and

places the controller in normal power mode, then the hardware follows the standard system reset procedure (see

Section 7.3.1.2).

7.3.1.2 System Reset Operation

Immediately following any type of system reset (Power-up reset, PWRGOOD reset, watchdog timer timeout,

lamp-strike reset), the DLPC4430 device automatically returns to NORMAL power mode in the following state:

• All GPIO are tri-stated.

• The Primary PLL remains active (it is reset only after a power-up reset sequence) and most of the derived

clocks are active. However, only those resets associated with the ARM9 processor and its peripherals are

released (the ARM9 is responsible for releasing all other resets).

• ARM9 associated clocks default to their full clock rates. (Boot-up is a full speed)

• All front end clocks derived are disabled.

DLPC4430

DLPS223 – DECEMBER 2021

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DLPC4430ZPC датащи(PDF) 26 Page - Texas Instruments