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PIC16F785 датащи(PDF) 13 Page - Microchip Technology

номер детали PIC16F785
подробное описание детали  20-Pin Flash-Based 8-Bit CMOS Microcontroller with Two-Phase Asychronous Feedback PWM, Dual High-Speed Comparators and Dual Operational Amplifiers
PDF  178 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F785 датащи(HTML) 13 Page - Microchip Technology

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 2004 Microchip Technology Inc.
Preliminary
DS41249A-page 11
PIC16F785
TABLE 2-2:
PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
22,110
01h
TMR0
Timer0 Module’s register
xxxx xxxx
47,110
02h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
21,110
03h
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
15,110
04h
FSR
Indirect data memory address pointer
xxxx xxxx
22,110
05h
PORTA(1)
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--x0 x000
33,110
06h
PORTB(1)
RB7
RB6
RB5
RB4
—
—
—
—
xx00 ----
40,110
07h
PORTC(1)
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
00xx 0000
43,110
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
0Ah
PCLATH
—
—
—
Write buffer for upper 5 bits of program counter
---0 0000
21,110
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
17,110
0Ch
PIR1
EEIF
ADIF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF
TMR1IF
0000 0000
19,110
0Dh
—
Unimplemented
—
—
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1
xxxx xxxx
49,110
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1
xxxx xxxx
49,110
10h
T1CON
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
0000 0000
51,110
11h
TMR2
Timer2 Module register
0000 0000
53,110
12h
T2CON
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
53,110
13h
CCPR1L
Capture/Compare/PWM Register1 Low Byte
xxxx xxxx
55,110
14h
CCPR1H
Capture/Compare/PWM Register1 High Byte
xxxx xxxx
55,110
15h
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
55,110
16h
—
Unimplemented
—
—
17h
—
Unimplemented
—
—
18h
WDTCON
—
—
—
WDTPS3
WDTPS2
WDTPS1
WDTPS0
SWDTEN
---0 1000
118,110
19h
—
Unimplemented
—
—
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
1Eh
ADRESH
Most Significant 8 bits of the left justified A/D result or 2 bits of right justified result
xxxx xxxx
79,110
1Fh
ADCON0
ADFM
VCFG
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
0000 0000
81,110
Legend:
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition. shaded = unimplemented
Note
1:
Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a reset even though the
data latches are either undefined (POR) or unchanged (other resets).



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