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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STP08CDC596TTR датащи(PDF) 9 Page - STMicroelectronics |
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STP08CDC596TTR датащи(HTML) 9 Page - STMicroelectronics |
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9 / 20 page  STP08CDC596 9/20 RUNNING THE DETECTION MODE Phase One: “Entering In Detection Mode” From the “Normal Mode” condition the device can switch to the “Error Detection Mode” by a logic sequence on the OE/DM2 and LE/DM1 pins as showed in the following Table and Diagram: Table 9: Entering In Detection Truth Table Figure 13: Entering In Detection Timing Diagram After these five CLK cycles the device goes into the” Error Detection Mode” and at the 6th rise front of CLK the SDI data are ready for the sampling. Phase Two: “Error Detection” The eight data bits must be set “1” in order to set ON all the outputs during the detection. The data are latched by LE/DM1 and after that the outputs are ready for the detection process. When the Micro controller switches the OE/DM2 to LOW, the device drives the LEDs in order to analyze if an OPEN or SHORT condition has occurred. Figure 14: Detection Diagram CLK 1° 2° 3° 4° 5° OE/DM2 H L H H H LE/DM1 L L L H L |
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