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AS3953B датащи(PDF) 30 Page - ams AG

номер детали AS3953B
подробное описание детали  14443 High Speed Passive Tag Interface
PDF  64 Pages
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производитель  AMSCO [ams AG]
домашняя страница  http://www.ams.com
Logo AMSCO - ams AG

AS3953B датащи(HTML) 30 Page - ams AG

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[v1-04] 2016-Jan-07
AS3953B − Application Information
SPI Interface
Communication between the AS3953B and controller is done
through a 4-wire Serial Peripheral Interface (SPI) and additional
interrupt signal. The AS3953B is an SPI slave device; it requests
controller attention by sending an interrupt (IRQ pin).
Figure 38:
SPI and Interrupt Signals
While signal /SS is high the SPI interface is in reset, while it is
low the SPI interface is enabled. It is recommended to keep
signal /SS high whenever the SPI interface is not in use. MOSI is
sampled at the falling edge of SCLK. All communication is done
in blocks of 8 bits (bytes). First three bits of first byte transmitted
after high to low transition of /SS define SPI operation mode.
MSB bit is always transmitted first (valid for address and data).
Read and Write modes support address auto incrementing,
which means that in case after the address and first data byte
some additional data bytes are sent (read), they are written to
(read from) addresses incremented by ‘1’.
SPI interface supports the following modes:
• Read and write of the SPI Interface internal registers
• Read and write of the EEPROM
• Read and write of the FIFO
• Sending direct commands
Please note that the only SPI operations, which are allowed
when logic and EEPROM are supplied from VP_SPI, are reading
and writing of EEPROM and registers (see also Power Manager)
Name
Signal
Signal Level
Description
/SS
Digital input with pull-up
CMOS
SPI enable (active low)
MOSI
Digital input
CMOS
Serial data input
MISO
Digital output with
tristate
CMOS
Serial data output
SCLK
Digital input
CMOS
Clock for serial communication
IRQ
Digital output
CMOS
Interrupt output pin
Application Information



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