FEDL7055-02

OKI Semiconductor

ML7055

11/30

DESCRIPTION OF INTERNAL BLOCKS

CLKGEN Block

• Generates a clock that is supplied to each block through SCLKP (12/13 MHz)

• STOP/HALT function

CTL/WDT Block

• Control of the frequency division function of the internal main clock

• Control of clock supplied to each peripheral

• Control of reset of each peripheral

• STOP/HALT control

• Watchdog timer function (interrupt/reset)

Timer Block

• 1 channel

• 18-bit timer counter

• Interrupt by compare function

• One shot, interval, or free-run mode

Base band Core Block

• RF Controller

- RF power supply control (PLL, TX, RX)

- Local PLL frequency division ratio setting

- Receive clock regeneration function

- Synchronization detection (synchronizing within the permissable error limit of SyncWord)

- Receive clock re-timing function

• FH Controller hopping

- Sequence control

- Frequency hopping selection function

- CRC computation's initial value selection function

Packet

Decomposer

FHCNT

RF

CNT

Packet

Composer

RF LSI

Tx SCO Buffer

Timing

Codec

I/F

ARM

I/F

RXD

TXD

Audio

APB

Tx ACL Buffer

Rx SCO Buffer

Rx ACL Buffer

Security

CNT