ADP2165ACPZ-1.2-R7 datasheet(20/23 Pages) AD

20 / 23 page

ADP2165/ADP2166

Data Sheet

Rev. B | Page 20 of 23

PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS

Good circuit board layout is essential for obtaining the best

performance from the ADP2165/ADP2166. Poor printed

circuit board (PCB) layout degrades the output regulation as

well as the electromagnetic interface (EMI) and electromagnetic

compatibility (EMC) performance. Figure 32 shows a PCB layout

example. For optimum layout, use the following guidelines:

•

Use separate analog ground and power ground planes.

Connect the ground reference of sensitive analog circuitry,

such as output voltage divider components, to analog

ground. In addition, connect the ground reference of

power components, such as input and output capacitors, to

power ground. Connect both ground planes to the exposed

pad of the ADP2165/ADP2166.

Place the input capacitor, inductor, and output capacitor as

close to the IC as possible and use short traces.

•

Ensure that the high current loop traces are as short and as

wide as possible. Make the high current path from the input

capacitor through the inductor, the output capacitor, and the

power ground plane back to the input capacitor as short as

possible. To accomplish this, ensure that the input and output

capacitors share a common power ground plane.

•

Connect the exposed pad of the ADP2165/ADP2166 to

a large copper plane to maximize its power dissipation

capability for better thermal dissipation.

Place the feedback resistor divider network as close as possible to

the FB pin to prevent noise pickup. Try to minimize the length of

the trace that connects the top of the feedback resistor divider

to the output while keeping the trace away from the high current

traces and the switching node to avoid noise pickup. To further

reduce noise pickup, place an analog ground plane on either side of

the FB trace and ensure that the trace is as short as possible to

reduce parasitic capacitance pickup.

GND

PGND

BST

PGND

PVIN

GND

RTOP

CVREG

ANALOG GROUND PLANE

POWER GROUND PLANE

VOUT

PVIN

CBST

INPUT

BULK

CAPACITOR

INPUT

BYPASS

CAPACITOR

INDUCTOR

OUTPUT

CAPACITOR

BOTTOM LAYER

TRACE

VIA

COPPER PLANE

AVIN

VREG

PULL-UP

PGOOD

POWER GROUND

PLANE

Figure 32. Recommended PCB Layout

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