ADP1048WARQZ-R7 datasheet(79/82 Pages) AD

79 / 82 page

Data Sheet

ADP1048W

Table 149. Register 0xFE82—Latched Flag 2

Bits

Bit Name

R/W

Description

[7:6]

RSVD

Reserved.

LOW_POWER

1 = input power has dropped below the threshold for low power mode operation.

FAST_LOOP

1 = fast loop compensation filter is in use.

VCORE_OV

1 = an overvoltage condition is present on the VCORE rail.

VDD_3.3V_OV

1 = an overvoltage condition is present on the VDD rail.

VDD_3.3V_UV

1 = an undervoltage condition is present on the VDD rail.

RSVD

Reserved.

PWM VALUE REGISTER

Table 150. Register 0xFE84—PWM Value

Bits

Bit Name

R/W

Description

[7:0]

PWM value

Return the eight MSBs of the PWM value (10 bits).

VAC_LINE_PERIOD REGISTER

Table 151. Register 0xFE85—VAC_LINE_PERIOD

Bits

Bit Name

R/W

Description

[7:0]

VAC line period

Return the measured period on the VAC pin signal. Each LSB corresponds to 163.84 μs.

READ TEMPERATURE ADC REGISTER

Table 152. Register 0xFE86—Read Temperature ADC

Bits

Bit Name

R/W

Description

[15:0]

RTD temperature

Return the measured temperature in ADC 13-bit format.

POWER METERING OFFSET TRIM FOR HIGH LINE INPUT REGISTER

Table 153. Register 0xFE8E—Power Metering Offset Trim for High Line Input

Bits

Bit Name

R/W

Description

Offset trim polarity

R/W

1 = negative offset trim is introduced.

0 = positive offset trim is introduced.

[6:0]

Power meter offset

trim

R/W

This value calibrates the power meter offset at the high line input voltage. Each LSB corresponds

to 0.0625/128 of the full input power.

POWER METERING GAIN TRIM FOR HIGH LINE INPUT REGISTER

Table 154. Register 0xFE8F—Power Metering Gain Trim for High Line Input

Bits

Bit Name

R/W

Description

Gain trim polarity

R/W

1 = negative gain trim is introduced.

0 = positive gain trim is introduced.

[6:0]

Power meter gain

trim

R/W

This value calibrates the power meter gain at the high line input voltage. Each LSB corresponds

to 0.0625/128 of the input power.

CURRENT LOOP FILTER GAIN FOR LOW LINE INPUT AND LIGHT LOAD REGISTER

Table 155. Register 0xFE90—Current Loop Filter Gain for Low Line Input and Light Load

Bits

Bit Name

R/W

Description

[7:0]

Current loop filter

gain for low line and

light load

R/W

These bits set the current loop digital filter gain of the PFC current loop under the low line

input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1.

Rev. 0 | Page 79 of 82

ADP1048WARQZ-R7 датащи(PDF) 79 Page - Analog Devices

ADP1048WARQZ-R7 датащи(HTML) 79 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

датащи скачать

ссылки URL