MPC8544EBVTARFA datasheet(13/117 Pages) NXP

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

Power Characteristics

The estimated typical core power dissipation for the core complex bus (CCB) versus the core frequency

for this family of PowerQUICC III devices is shown in Table 4.

Input Clocks

This section contains the following subsections:

•

Section 4.1, “System Clock Timing”

•

Section 4.2, “Real-Time Clock Timing”

•

Section 4.3, “eTSEC Gigabit Reference Clock Timing”

•

Section 4.4, “Platform to FIFO Restrictions”

•

Section 4.5, “Other Input Clocks”

Table 4. MPC8544ECore Power Dissipation

Power Mode

Core Frequency

(MHz)

Platform Frequency

(MHz)

VDD

(V)

Junction

Temperature (

°C)

Power

(W)

Notes

Typical

667

333

1.0

2.6

1, 2

Thermal

105

4.5

1, 3

Maximum

7.15

1, 4

Typical

800

400

1.0

2.9

1, 2

Thermal

105

4.8

1, 3

Maximum

7.35

1, 4

Typical

1000

400

1.0

3.6

1, 2

Thermal

105

5.3

1, 3

Maximum

7.5

1, 4

Typical

1067

533

1.0

3.9

1, 2

Thermal

105

6.0

1, 3

Maximum

7.7

1, 4

Notes:

1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and

configurations. The values do not include power dissipation for I/O supplies.

2. Typical power is an average value measured at the nominal recommended core voltage (VDD) and 65°C junction temperature

(see Table 2) while running the Dhrystone 2.1 benchmark.

3. Thermal power is the average power measured at nominal core voltage (VDD) and maximum operating junction temperature

(see Table 2) while running the Dhrystone 2.1 benchmark.

4. Maximum power is the maximum power measured at nominal core voltage (VDD) and maximum operating junction

temperature (see Table 2) while running a smoke test which includes an entirely L1-cache-resident, contrived sequence of

instructions which keep the execution unit maximally busy.

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