MPC8533EVJALGA datasheet(31/112 Pages) NXP

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MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.5.1

TBI Transmit AC Timing Specifications

Table 29 provides the TBI transmit AC timing specifications.

Figure 15 shows the TBI transmit AC timing diagram.

Figure 15. TBI Transmit AC Timing Diagram

8.5.2

TBI Receive AC Timing Specifications

Table 30 provides the TBI receive AC timing specifications.

Table 29. TBI Transmit AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

GTX_CLK clock period

tGTX

—8.0

—

GTX_CLK to TCG[9:0] delay time

tTTKHDX

0.2

—

5.0

GTX_CLK rise (20%–80%)

tTTXR

——

1.0

—

GTX_CLK fall time (80%–20%)

tTTXF

——

1.0

—

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI

transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid

state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going

high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript

of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. Data valid tTTKHDV to GTX_CLK Min setup time is a function of clock period and max hold time (Min setup = cycle time – Max

delay).

Table 30. TBI Receive AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

PMA_RX_CLK[0:1] clock period

tTRX

—

16.0

—

PMA_RX_CLK[0:1] skew

tSKTRX

7.5

—

8.5

—

GTX_CLK

TCG[9:0]

tTTX

tTTXH

tTTXR

tTTXF

tTTKHDV

tTTKHDX

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