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ADUCM4050BCBZ-R7 датащи(PDF) 36 Page - Analog Devices

номер детали ADUCM4050BCBZ-R7
подробное описание детали  Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management
PDF  46 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADUCM4050BCBZ-R7 датащи(HTML) 36 Page - Analog Devices

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ADuCM4050
Data Sheet
Rev. A | Page 36 of 46
DEVELOPMENT SUPPORT
Development support for the ADuCM4050 MCU includes
documentation, evaluation hardware, and development
software tools.
Documentation
The ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU
with Integrated Power Management Hardware Reference details
the functionality of each block on the ADuCM4050 MCU. It
includes power management, clocking, memories, and peripherals.
The ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU
with Integrated Power Management Hardware Reference can be
ordered from any Analog Devices sales office or accessed
electronically on the Analog Devices website at www.analog.com.
Hardware
The EV-COG-AD4050LZ is available to prototype sensor
configuration with the ADuCM4050 MCU.
Software
The EV-COG-AD4050LZ includes a complete development and
debug environment for the ADuCM4050 MCU. The device
family pack for the ADuCM4050 MCU is provided for the IAR
Embedded Workbench for ARM, Keil™, and CrossCore®
embedded studio (CCES) environments.
The device family pack also includes operating system (OS)
aware drivers and example code for peripherals on the device.
REFERENCE DESIGNS
The Circuits from the Lab® web page provides the following for
the ADuCM4050 reference design:
Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
Drill down links for components in each chain to selection
guides and application information
Reference designs applying best practice design techniques
SECURITY FEATURES DISCLAIMER
To the knowledge of Analog Devices, the security features,
when used in accordance with the data sheet and hardware
reference manual specifications, provide a secure method of
implementing code and data safeguards. However, Analog
Devices does not guarantee that this technology provides
absolute security. Accordingly, analog devices hereby disclaims
any and all express and implied warranties that the security
features cannot be breached, compromised, or otherwise
circumvented and in no event is Analog Devices liable for any
loss, damage, destruction, or release of data, information,
physical property, or intellectual property.
MCU TEST CONDITIONS
The ac signal specifications (timing parameters) appearing in
this data sheet include output disable time, output enable time,
and others. Timing is measured on signals when they cross the
voltage threshold (VMEAS ) level as described in Figure 24. All
delays (in nanoseconds or microseconds) are measured between
the point that the first signal reaches VMEAS and the point that
the second signal reaches VMEAS. The value of VMEAS is set to
VBAT/2. The tester pin electronics is shown in Figure 25.
INPUT
OR
OUTPUT
VMEAS
VMEAS
Figure 24. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
VLOAD
NOTES
1. THE WORST-CASE TRANSMISSION LINE DELAY (TD) IS SHOWN AND
CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE
TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED.
TRANSMISSION LINE IS FOR LOAD ONLY AND DOES NOT AFFECT
THE DATA SHEET TIMING SPECIFICATIONS.
2. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING
FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM
CAN INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR
ANY TIMING DIFFERENCES.
50Ω
70Ω
45Ω
ZO = 50Ω (IMPEDANCE)
TD = 4.04ns ± 1.18ns
50Ω
400Ω
2pF
0.5pF
4pF
DUT
OUTPUT
T1
Figure 25. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
DRIVER TYPES
Table 27 shows the driver types.
Table 27. Driver Types
DriverType1,2,3 Associated Pins
Type A
P0_00 to P0_03, P0_07, P0_10 to P0_13, P0_15,
P1_00 to P1_10, P1_15, P2_00, P2_01, P2_04 to
P2_14, P3_00 to P3_03, and SYS_HWRST
Type B
P0_08, P0_09, P0_14, P1_11 to P1_14, and P2_02
Type C
P0_04 and P0_05
Type D
P0_06
1
In single drive mode, the maximum source/sink capacity is 2 mA.
2
In double drive mode, the maximum source/sink capacity is 4 mA.
3
At maximum drive capacity, only 16 GPIOs are allowed to switch at any given
point in time.



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