MAX96708 datasheet(18/68 Pages) MAXIM

18 / 68 page

NAME

FUNCTION

REF SUPPLY

TYPE

POWER

AVDD

1.8V Analog Power Supply. Bypass AVDD to EP with 0.1μF and

0.001μF capacitors placed as close as possible to the device, with

the smaller-value capacitor closest to AVDD.

Power

DVDD

1.8V Digital Power Supply. Bypass DVDD to EP with 0.1μF and

0.001μF capacitors placed as close as possible to the device, with

the smaller-value capacitor closest to DVDD.

Power

IOVDD

I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass

IOVDD to EP with 0.1μF and 0.001μF capacitors placed as close

as possible to the device, with the smaller-value capacitor closest

to IOVDD.

Power

—

Exposed Pad. EP is internally connected to device ground. Must

connect EP to the PCB ground plane through a via array for proper

thermal and electrical performance.

Power

HIGH-SPEED DIGITAL

High-Speed Digital / Multifunction

DOUT13/VS

Parallel-Data/Vertical-Sync Output. Defaults to parallel-data

output on power-up. Vertical-sync output when HS/VS encoding is

enabled.

IOVDD

Digital

DOUT12/HS

Parallel-Data/Horizontal-Sync Output. Defaults to parallel-data

output on power-up. Horizontal-sync output when HS/VS encoding

is enabled.

IOVDD

Digital

DOUT11/

CXTP/DE

Parallel-Data Output/Cable-Type Input/Data-Enable Output with

internal pulldown to EP. CX/TP is latched at power-up, or when

resuming from power-down mode (PWDNB = low), and switches

to parallel/data-enable output after power-up. Connect CXTP to

IOVDD with a 30kΩ resistor to set high (coax mode), or leave open

to set low (twisted-pair mode).

IOVDD

Digital

DOUT10/

I2CSEL

Parallel-Data Output/I2C-Select Input with Internal Pulldown to EP.

I2CSEL is latched at power-up, or when resuming from power-

down mode (PWDNB = low), and switches to parallel-data output

after power-up. Connect I2CSEL to IOVDD with a 30kΩ resistor to

set high (I2C interface), or leave open to set low (UART interface).

IOVDD

Digital

DOUT9/

ADD3

Parallel-Data Output/Address Input with Internal Pulldown to EP.

ADD3 is latched at power-up, or when resuming from power-down

mode (PWDNB = low), and switches to parallel-data output after

power-up. Connect ADD3 to IOVDD with a 30kΩ resistor to set

high, or leave open to set low.

IOVDD

Digital

DOUT8/

ADD2

Parallel-Data Output/Address Input with Internal Pulldown to EP.

ADD2 is latched at power-up, or when resuming from power-down

mode (PWDNB = low), and switches to parallel-data output after

power-up. Connect ADD2 to IOVDD with a 30kΩ resistor to set

high, or leave open to set low.

IOVDD

Digital

Pin Description

www.maximintegrated.com

Maxim Integrated │ 18

MAX96708

14-Bit GMSL Deserializer

with Coax or STP Cable Input

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