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SH7041A датащи(PDF) 282 Page - Renesas Technology Corp |
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SH7041A датащи(HTML) 282 Page - Renesas Technology Corp |
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282 / 923 page ![]() 244 11.3.7 Bus Modes Select the appropriate bus mode in the TM bits of CHCR0–CHCR3. There are two bus modes: cycle steal and burst. Cycle-Steal Mode: In the cycle steal mode, the bus right is given to another bus master after each one-transfer-unit (byte, word, or longword) DMAC transfer. When the next transfer request occurs, the bus rights are obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. The cycle steal mode can be used with all categories of transfer destination, transfer source and transfer request. Figure 11.12 shows an example of DMA transfer timing in the cycle steal mode. Transfer conditions are dual address mode and DREQ level detection. CPU CPU CPU DMAC DMAC CPU DMAC DMAC CPU CPU DREQ Bus cycle Bus control returned to CPU Read Write Write Read Figure 11.12 DMA Transfer Example in the Cycle-Steal Mode Burst Mode: Once the bus right is obtained, the transfer is performed continuously until the transfer end condition is satisfied. In the external request mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus passes to the other bus master after the bus cycle of the DMAC that currently has an acknowledged request ends, even if the transfer end conditions have not been satisfied. Figure 11.13 shows an example of DMA transfer timing in the burst mode. Transfer conditions are single address mode and DREQ level detection. CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DREQ Bus cycle DMAC CPU Figure 11.13 DMA Transfer Example in the Burst Mode |
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