SH7041A datasheet(249/923 Pages) RENESAS

номер детали	SH7041A

подробное описание детали	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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Cycles in which Bus is not Released

(a) One bus cycle:

The bus is never released during a single bus cycle. For example, in the case of a longword read

(or write) in 8-bit normal space, the four memory accesses to the 8-bit normal space constitute a

single bus cycle, and the bus is never released during this period. Assuming that one memory

access requires two states, the bus is not released during an 8-state period.

8 bit

Cycles in which

Bus is not Released

Figure 10.32 One Bus Cycle

10.10

CPU Operation when Program is in External Memory

In the SH7040 Series, two words (equivalent to two instructions) are normally fetched in a single

instruction fetch. This is also true when the program is located in external memory, irrespective of

whether the external memory bus width is 8 or 16 bits.

If the program counter value immediately after the program branches is an odd-word (2n + 1)

address, or if the program counter value immediately before the program branches is an even-word

(2n) address, the CPU will always fetch 32 bits (equivalent to two instructions) that include the

respective word instruction.

SH7041A датащи(PDF) 249 Page - Renesas Technology Corp