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SH7041A датащи(PDF) 215 Page - Renesas Technology Corp |
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SH7041A датащи(HTML) 215 Page - Renesas Technology Corp |
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215 / 923 page ![]() 177 • Bits 7–4—CS1 Space Wait Specification (W13, W12, W11, W10): Specifies the number of waits for CS1 space access. Bit 7 (W13) Bit 6 (W12) Bit 5 (W11) Bit 4 (W10) Description 0000 No wait (external wait input disabled) 0001 1 wait external wait input enabled ⋅⋅⋅ 1111 15 wait external wait input enabled (initial value) • Bits 3–0—CS0 Space Wait Specification (W03, W02, W01, W00): Specifies the number of waits for CS0 space access. Bit 3 (W03) Bit 2 (W02) Bit 1 (W01) Bit 0 (W00) Description 0000 No wait (external wait input disabled) 0001 1 wait external wait input enabled ⋅⋅⋅ 1111 15 wait external wait input enabled (initial value) 10.2.4 Wait Control Register 2 (WCR2) WCR2 is a 16-bit read/write register that specifies the number of access cycles for DRAM space and CS space for DMA single address mode transfers. Do not perform any DMA single address transfers before WCR2 is set. WCR2 is initialized by power-on resets to H'000F, but is not initialized by manual resets or software standbys. Bit: 15 14 13 12 11 10 9 8 —— —— ——— — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — DDW1 DDW0 DSW3 DSW2 DSW1 DSW0 Initial value: 0 0 0 0 1 1 1 1 R/W: R R R/W R/W R/W R/W R/W R/W |
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