SH7041A datasheet(209/923 Pages) RENESAS

номер детали	SH7041A

подробное описание детали	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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производитель	RENESAS [Renesas Technology Corp]

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• Bit 6—CS2 Space Long Size Specification (A2LG): Specifies the CS2 space bus size.

Bit 6 (A2LG)

Description

According to the A2SZ bit value (initial value)

Longword (32 bit) size

• Bit 5—CS1 Space Long Size Specification (A1LG): Specifies the CS1 space bus size.

Bit 5 (A1LG)

Description

According to the A1SZ bit value (initial value)

Longword (32 bit) size

• Bit 4—CS0 Space Long Size Specification (A0LG): Specifies the CS0 space bus size.

Bit 4 (A0LG)

Description

According to the A0SZ bit value (initial value)

Longword (32 bit) size

Note:

A0LG is effective only in on-chip ROM effective mode. When in on-chip ROM ineffective

mode, the CS0 space bus size is specified by the mode pin.

• Bit 3—CS3 Space Size Specification (A3SZ): Specifies the CS3 space bus size when A3LG =

0. This is effective only when CS3 space is ordinary space. When CS3 space is an address/data

multiplex I/O space, bus size is decided by the A14 bit.

Bit 3 (A3SZ)

Description

Byte (8 bit) size

Word (16 bit) size (initial value)

Note:

This bit is ignored when A3LG = 1; CS3 space bus size becomes longword (32 bit) (for

ordinary space).

• Bit 2—CS2 Space Size Specification (A2SZ): Specifies the CS2 space bus size when A2LG =

Bit 2 (A2SZ)

Description

Byte (8 bit) size

Word (16 bit) size (initial value)

Note:

This bit is ignored when A2LG = 1; CS2 space bus size becomes longword (32 bit).

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