поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

SH7041A датащи(PDF) 195 Page - Renesas Technology Corp

номер детали SH7041A
подробное описание детали  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A датащи(HTML) 195 Page - Renesas Technology Corp

Back Button SH7041A Datasheet HTML 191Page - Renesas Technology Corp SH7041A Datasheet HTML 192Page - Renesas Technology Corp SH7041A Datasheet HTML 193Page - Renesas Technology Corp SH7041A Datasheet HTML 194Page - Renesas Technology Corp SH7041A Datasheet HTML 195Page - Renesas Technology Corp SH7041A Datasheet HTML 196Page - Renesas Technology Corp SH7041A Datasheet HTML 197Page - Renesas Technology Corp SH7041A Datasheet HTML 198Page - Renesas Technology Corp SH7041A Datasheet HTML 199Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 195 / 923 page
background image
157
Table 9.1
Register Configuration
Name
Abbreviation
R/W
Initial
Value
Address
Access Size
(Bits)
Cache control register
CCR
R/W
H'0000*
H'FFFF8740
8, 16, 32
Note: * Bits 15–5 are undefined.
9.2
Register Explanation
9.2.1
Cache Control Register (CCR)
The cache control register (CCR) selects the cache enable/disable of each space.
The CCR is a 16-bit readable/writable register. It is initialized to H'0000 by power on resets, but is
not initialized by manual resets or standby mode.
Bit:
15
14
13
12
11
10
9
8
——
——
———
—
Initial value:
**
**
***
*
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
——
—
CE
DRAM
CE
CS3
CE
CS2
CE
CS1
CE
CS0
Initial value:
**
*
0
000
0
R/W:
R
R
R
R/W
R/W
R/W
R/W
R/W
Note: * Bits 15–5 are undefined.
• Bits 15–5—Reserved: Reading these bits gives undefined values. The write value should
always be 0.
• Bit 4—DRAM Space Cache Enable (CEDRAM): Selects whether to use DRAM space as a
cache object (enable) or to exclude it (disable). A 0 disables, and a 1 enables such use.
Bit 4 (CEDRAM)
Description
0
DRAM space cache disabled (initial value)
1
DRAM space cache enabled



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com