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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SH7041A датащи(PDF) 162 Page - Renesas Technology Corp |
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SH7041A датащи(HTML) 162 Page - Renesas Technology Corp |
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162 / 923 page  124 Bit: 15 14 13 12 11 10 9 8 —— —— ——— — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 CP1 CP0 ID1 ID0 RW1 RW0 SZ1 SZ0 Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bits 15–8—Reserved: These bits always read as 0. The write value should always be 0. • Bits 7 and 6—CPU Cycle/Peripheral Cycle Select (CP1, CP0): These bits designate break conditions for CPU cycles or peripheral cycles (DMA/DTC cycles). Bit 7: CP1 Bit 6: CP0 Description 0 0 No user break interrupt occurs (initial value) 1 Break on CPU cycles 1 0 Break on peripheral cycles 1 Break on both CPU and peripheral cycles • Bits 5 and 4—Instruction Fetch/Data Access Select (ID1, ID0): These bits select whether to break on instruction fetch and/or data access cycles. Bit 5: ID1 Bit 4: ID0 Description 0 0 No user break interrupt occurs (initial value) 1 Break on instruction fetch cycles 1 0 Break on data access cycles 1 Break on both instruction fetch and data access cycles |
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