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SH7041A датащи(PDF) 148 Page - Renesas Technology Corp

номер детали SH7041A
подробное описание детали  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A датащи(HTML) 148 Page - Renesas Technology Corp

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110
• Bit 8—NMI Edge Select (NMIE)
Bit 8: NMIE
Description
0
Interrupt request is detected on falling edge of NMI input (initial value)
1
Interrupt request is detected on rising edge of NMI input
• Bits 7–0—IRQ0–IRQ7 Sense Select (IRQ0S–IRQ7S): These bits set the IRQ0–IRQ7 interrupt
request detection mode.
Bits 7-0: IRQ0S–IRQ7S
Description
0
Interrupt request is detected on low level of IRQ input (initial value)
1
Interrupt request is detected on falling edge of IRQ input
6.3.3
IRQ Status Register (ISR)
The ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input
pins
IRQ0–IRQ7. When IRQ interrupts are set to edge detection, held interrupt requests can be
withdrawn by writing a 0 to IRQnF after reading an IRQnF = 1.
A power-on reset initializes ISR but the standby mode does not.
Bit:
15
14
13
12
11
10
9
8
——
——
———
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
IRQ0F
IRQ1F
IRQ2F
IRQ3F
IRQ4F
IRQ5F
IRQ6F
IRQ7F
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Bits 15–8—Reserved: These bits always read as 0. The write value should always be 0.



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