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SH7041A датащи(PDF) 464 Page - Renesas Technology Corp

номер детали SH7041A
подробное описание детали  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A датащи(HTML) 464 Page - Renesas Technology Corp

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426
(13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is
Restarted in Normal Mode: Figure 12.108 shows an explanatory diagram of the case where an
error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
1
RESET
2
TMDR
(PWM2)
3
TIOR
(1 init
0 out)
5
TSTR
(1)
4
PFC
(MTU)
6
Match
7
Error
occurs
8
PFC
(PORT)
9
TSTR
(0)
10
TMDR
(normal)
11
TIOR
(1 init
0 out)
12
PFC
(MTU)
13
TSTR
(1)
MTU output
TIOC*A
TIOC*B
Port output
PEn
PEn
• Not initialized (cycle register)
n=0 to 15
High-Z
High-Z
Figure 12.108 Error Occurrence in PWM Mode 2, Recovery in Normal Mode
1.After a reset, MTU output is low and ports are in the high-impedance state.
2.Set PWM mode 2.
3. Initialize the pins with TIOR.
(The example shows initial high output, with low output on
compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the
example, TIOC *A is the cycle register.)
4.Set MTU output with the PFC.
5.The count operation is started by TSTR.
6.Output goes low on compare-match occurrence.
7.An error occurs.
8.Set port output with the PFC and output the inverse of the active level.
9.The count operation is stopped by TSTR.
10.Set normal mode.
11.Initialize the pins with TIOR.
12.Set MTU output with the PFC.
13.Operation is restarted by TSTR.



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