SH7041A datasheet(359/923 Pages) RENESAS

номер детали	SH7041A

подробное описание детали	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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производитель	RENESAS [Renesas Technology Corp]

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12.2.14

Timer Dead Time Data Register (TDDR)

The timer dead time data register (TDDR) is a 16-bit register, used only in complementary PWM

mode, that specifies the TCNT3 and TCNT4 counter offset values. In complementary PWM mode,

when the TCNT3 and TCNT4 counters are cleared and then restarted, the TDDR register value is

loaded into the TCNT3 counter and the count operation starts. The TDDR register is initialized to

H'FFFF by a power-on reset or in standby mode. Manual reset does not initialize TDDR.

Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units.

Bit:

Initial value:

R/W:

R/W

Bit:

Initial value:

R/W:

R/W

12.2.15

Timer Period Data Register (TCDR)

The timer period data register (TCDR) is a 16-bit register used only in complementary PWM

mode. Set the PWM carrier sync value as the TCDR register value. This register is constantly

compared with the TCNTS counter in complementary PWM mode, and when a match occurs the

TCNTS counter switches direction (decrement to increment).

The TCDR register is initialized to H'FFFF by a reset or in standby mode. Manual reset does not

initialize TCDR. Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units.

Bit:

Initial value:

R/W:

R/W

Bit:

Initial value:

R/W:

R/W

SH7041A датащи(PDF) 359 Page - Renesas Technology Corp