LTC4012 datasheet(11/52 Pages) AD

11 / 52 page

LTC4162-L

Rev A

For more information www.analog.com

PIN FUNCTIONS

CELLS0 (Pin 17): Cell count selection pin. Used in com-

bination with CELLS1, this pin sets the total number of

series cells to be charged. The pin should be strapped to

either INTVCC, VCC2P5 or GND to represent one of three

possible states. See Table 5.

CELLS1 (Pin 18): Cell count selection pin. Used in com-

bination with CELLS0, this pin sets the total number of

series cells to be charged. The pin should be strapped to

either INTVCC, VCC2P5 or GND to represent one of three

possible states. See Table 5.

BATSENS+ (Pin 19): Positive terminal battery sense pin.

BATSENS+shouldKelvinsensethepositiveterminalofthe

battery for optimized charging. A 10µF multilayer ceramic

capacitor is required from BATSENS+ to ground.

CSN (Pin 20): Connection point for the negative terminal

of the current sense resistor used to measure and limit

charge current.

CSP (Pin 21): Connection point for the positive terminal

of the current sense resistor used to measure and limit

charge current.

BATFET (Pin 22): Gate control pin for a reverse blocking

externalN-channelMOSFETbetweenthebatteryandVOUT.

PGND(Pins23,24):Powergroundpins.Thesepinsshould

be connected to a copper pour that forms the return for

the VOUT bypass capacitor on the top layer of the printed

circuit board.

SW (Pin 25, 26): Switching regulator power transmission

pins. The SW pins deliver power from the VOUT pins to the

battery via the step-down switching regulator. An inductor

should be connected from SW to a sense resistor at CSP.

See the Applications Information section for a discussion

of inductor value and current rating.

VOUT (Pin 27, 28): Switching regulator input pins. The

VOUT pins deliver power to the switching charger. Having

extremely high frequency current pulses, bypassing of

the VOUT pins should take precedence over all other PCB

layout considerations. A bypass capacitor of 10µF is a

good starting point.

AGND (Exposed PAD, Pin 29): Analog ground pin. This

is the ground pin used to return all of the analog circuitry

inside the LTC4162 and should be connected to an analog

ground pour that is common with PGND (pins 23 and 24).

It should also be connected to a ground plane on layer 2

of the PCB to which all of the analog components return

such as the RT resistor and the INTVCC and VCC2P5 by-

pass capacitors.

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