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PD70210AL датащи(PDF) 15 Page - Microchip Technology |
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PD70210AL датащи(HTML) 15 Page - Microchip Technology |
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15 / 31 page ![]() 3. Pin Configuration The following illustration shows the device pin diagram from the top views. Figure 3-1. Pin Diagram The following table lists the pin descriptions of the PD70101/PD70201 device. Table 3-1. Pin Descriptions Pin Number PD70101 Pin Name PD70201 Pin Name Description 1 RDET RDET Valid Detection Resistor: Connect a 24.9 kΩ, 1% resistor from this pin to VPP. 2 PGOOD PGOOD Open Drain Output (active low): This flag is generated to indicate the power rails (VPN_OUT) are ready. 3 RREF RREF Bias current resistor for the PD Interface. Connect a 240k 1% resistor between this pin and VPN_IN. 4 RCLASS RCLASS Power Classification Setting: Connect external class resistor between this pin and VPN_IN. 5 VPN_IN VPN_IN VPort Negative Input: Connected to the isolating switch input N-channel MOSFET source. 6 N/C N/C Not used. 7 N/C AT_FLAG Open Drain Output (active low): This flag indicates if the chip detects an IEEE 802.3at compliant PSE. 8 VPN_OUT VPN_OUT VPort Negative Output: Connected to the isolating switch output. N-channel MOSFET Drain. 9 N/C N/C Not Used. 10 ENABLE ENABLE Logic level Enable input for DC-DC controller. Pulling this pin to VL turns on the DC-DC controller. This allows the DC- DC controller to be turned on without power to the PD interface. PD70101 and PD70201 Pin Configuration © 2020 Microchip Technology Inc. Datasheet DS00003738A-page 15 |
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