Burst Mode

Burst mode allows multiple SRAM locations to be

loaded at high speed. During burst mode, the output

voltages are not updated until the data burst is com-

plete and control returns to the sequencer. Select burst

mode by driving both IMMED and C1 low.

The sequencer is interrupted when CS is taken low. All

or part of the memory can be loaded while CS is low.

Each data word is loaded into its specified SRAM

address. The DAC conversion and SHA sample in

progress are completely transparent to the serial bus

activity. When CS is taken high, the sequencer resumes

scrolling at the interrupted SRAM address. New values

are updated when their turn comes up in the sequence.

After burst mode is used, it is recommended that at

least one full sequencer loop (320µs) is allowed to

occur before the serial port is accessed again. This

ensures that all outputs are updated before the

sequencer is interrupted.

Figure 6 shows an example of a burst-mode operation.

As with the immediate-update example, CS falls while

channel 7 is being refreshed. Data for multiple chan-

nels is loaded, and no channels are refreshed as long

as CS remains low. Once CS returns high, sequencing

resumes with channel 7 and continues normal refresh

all channels have been updated.

External Sequencer Clock

An external clock may be used to control the sequencer,

altering the output update rate. The sequencer runs at

1/4 the frequency of the supplied clock (ECLK). The

external clock option is selected by driving either C0 or

CLKSEL high.

When CLKSEL is asserted, the internal clock oscillator

is disabled. This feature allows synchronizing the

sequencer to other system operations, or shutting down

of the sequencer altogether during high-accuracy sys-

tem measurements. The low 1µV/ms droop of these

devices ensures that no appreciable degradation of the

output voltages occurs, even during extended periods

of time when the sequencer is disabled.

Power-On Reset

A power-on reset (POR) circuit sets all channels to 0V

(code 4F3 hex) in sequence, requiring 320µs. This pre-

vents damage to downstream ICs due to arbitrary refer-

ence levels being presented following system power-up.

This same function is available by driving RST low.

During the reset operation, the sequencer is run by the

internal clock, regardless of the state of CLKSEL. The

reset process cannot be interrupted, serial inputs are

ignored until the entire reset process is complete.

Applications Information

Power Supplies and Bypassing

Grounding and power-supply decoupling strongly influ-

ence device performance. Digital signals can couple

through the reference input, power supplies, and

ground connection. Proper grounding and layout can

reduce digital feedthrough and crosstalk. At the device

pins as possible. More substantial decoupling at the

board level is recommended and is dependent on the

number of devices on the board (Figure 7).

The MAX5331/MAX5332/MAX5333 have three separate

interface, sequencer, internal clock, and SRAM.

overall performance of the device.

Chip Information

TRANSISTOR COUNT: 16,229

PROCESS: BiCMOS

12-Bit DACs with 32-Channel

Sample-and-Hold Outputs

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