DS2152 datasheet(49/97 Pages) MAXIM

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DS2152

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8.2 Hardware-Based Signaling

8.2.1 Receive Side

In the receive side of the hardware based signaling, there are two operating modes for the signaling

buffer: signaling extraction and signaling reinsertion. Signaling extraction involves pulling the signaling

bits from the receive data stream and buffering them over a four multiframe buffer and outputting them in

a serial PCM fashion on a channel-by-channel basis at the RSIG output. This mode is always enabled. In

this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, then

the backplane clock (RSYSCLK) can be either 1.544MHz or 2.048MHz. In the ESF framing mode, the

ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated

once a multiframe (3ms) unless a freeze is in effect. In the D4 framing mode, the AB signaling bits are

output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as

bits 7 and 8, respectively, in each channel. The RSIG data is updated once a multiframe (1.5ms) unless a

freeze is in effect. See the timing diagrams in Section 16 for some examples.

The other hardware-based signaling operating mode called signaling reinsertion can be invoked by setting

the RSRE control bit high (CCR4.7 = 1). In this mode, the user will provide a multiframe sync at the

RSYNC pin and the signaling data will be re-aligned at the RSER output according to this applied

multiframe boundary. In this mode, the elastic store must be enabled however the backplane clock can be

either 1.544MHz or 2.048MHz.

If the signaling reinsertion mode is enabled, the user can control which channels have signaling

reinsertion performed on a channel-by-channel basis by setting the RPCSI control bit high (CCR4.6) and

then programming the RCHBLK output pin to go high in the channels in which the signaling reinsertion

should not occur. If the RPCSI bit is set low, then signaling reinsertion will occur in all channels when

the signaling reinsertion mode is enabled (RSRE = 1). How to control the operation of the RCHBLK

output pin is covered in Section 10. In signaling reinsertion mode, the user has the option to replace all of

the extracted robbed-bit signaling bit positions with 1s. This option is enabled via the RFSA1 control bit

(CCR4.5) and it can be invoked on a per-channel basis by setting the RPCSI control bit (CCR4.6) high

and then programming RCHBLK appropriately just like the per-channel signaling reinsertion operates.

The signaling data in the four-multiframe buffer will be frozen in a known good state upon either a loss of

synchronization (OOF event), carrier loss, or frame slip. This action meets the requirements of BellCore

TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RFE control bit

(CCR4.4) should be set high. The user can force a freeze by setting the RFF control bit (CCR4.3) high.

The RSIGF output pin provides a hardware indication that a freeze is in effect. The four-multiframe

buffer provides a three-multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER

pin if RSRE = 1). When freezing is enabled (RFE = 1), the signaling data will be held in the last known

good state until the corrupting error condition subsides. When the error condition subsides, the signaling

data will be held in the old state for at least an additional 9ms (or 4.5ms in D4 framing mode) before

being allowed to be updated with new signaling data.

8.2.2 Transmit Side

Via the THSE control bit (CCR4.2), the DS2152 can be set up to take the signaling data presented at the

TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The

user can control which channels are to have signaling data from the TSIG pin inserted into them on a

channel-by-channel basis by setting the TPCSI control bit (CCR4.1) high. When TPCSI is enabled,

channels in which the TCHBLK output has been programmed to be set high in, will not have signaling

data from the TSIG pin inserted into them. The hardware signaling insertion capabilities of the DS2152

are available whether the transmit side elastic store is enabled or disabled. If the elastic store is enabled,

the backplane clock (TSYSCLK) can be either 1.544 MHz or 2.048 MHz.

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