PAC1934 datasheet(27/64 Pages) MICROCHIP

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DS20005850E-page 27

PAC1931/2/3/4

5.2

SMBus Time-Out

The PAC1931/2/3/4 can support the SMBus Time-Out

functionality. This functionality is disabled by default,

and can be enabled by writing to the Timeout bit (see

1Ch).

If Time-Out is enabled and the clock is held at logic ‘0’

for tTIMEOUT = 25-43 ms, the device will time-out and

reset the SMBus interface. Communication is restored

with a start condition.

5.3

SMBus and I2C Compatibility

The PAC1931/2/3/4 is compatible with SMBus 3.0

1 MHz class and I2C Fast-mode Plus. The major

differences between SMBus and I2C devices are

highlighted here. For more information, refer to the

SMBus 3.0 and I2C specifications.

If Time-Out function is enabled, the minimum

frequency for SMBus communications is

10 kHz. If Time-Out function is disabled (default

condition), then there is no minimum frequency

for SMBus communications.

If SMBus Time-Out is enabled in Register 6-10:

CHANNEL_DIS and SMBus (Address 1Ch),the

SMBus slave protocol will reset if the clock is

held at a logic ‘0’ for tTIMEOUT. I2C does not have

a time-out, this is the default condition.

I2C devices do not support the Alert Response

Address functionality (which is optional for

SMBus).The PAC1931/2/3/4 does not support

the Alert Response Address functionality;

instead, the ALERT is a GPIO pin that may be

monitored by the master or Embedded

Controller.

I2C devices support Block Read and Block Write

differently. I2C protocol allows for unlimited

number of bytes to be sent in either direction.

The SMBus protocol for Block Read and Block

Write requires that an additional data byte

indicating number of bytes to read/write is

transmitted. PAC1931/2/3/4 devices support the

I2C protocol for Block Read by default (no byte

count information is sent). If the Byte Count bit is

set (see Register 6-10: CHANNEL_DIS and

SMBus (Address 1Ch), it will be sent as the first

data byte in response to the Block Read

command, per SMBus protocol.

5.4

I2C/SMBus Protocols

The PAC1931/2/3/4 supports Write Byte, Read Byte,

Block Read, Send Byte and Receive Byte as valid

protocols.

It will not respond to the Alert Response Address

protocol. It will respond to the I2C General Call

Address.

All of the protocol charts listed below use the

convention in Table 5-2.

5.5

Auto-Incrementing Pointer

The PAC1931/2/3/4 has an auto-incrementing address

pointer. The pointer has two loops for auto-incrementing,

a read loop and a write loop.

The read loop includes all of the readable registers,

including all of the configuration and Control registers,

the results registers, and the Product ID, Manufacturer

ID and Revision ID registers.

The write loop includes only the writable control and

configuration registers.

Neither loop includes the REFRESH commands.

The read loop will skip inactive channels, if some

channels have been disabled. This automatic channel

skipping feature can be disabled by setting the No Skip

bit in Register 6-10: CHANNEL_DIS and SMBus

(Address 1Ch).

If the user elects to read disabled channels, they will

return FFh and the register address will by NACKed.

See Figure 5-1 for a graphic representation.

TABLE 5-2:

PROTOCOL FORMAT

Data Sent to Device

Data Sent to the Master

# of bits sent

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