853210AY

www.icst.com/products/hiperclocks.html

REV. A NOVEMBER 12, 2003

7

Integrated

Circuit

Systems, Inc.

ICS853210

Figure 1A shows an example of the differential input that can

be wired to accept single ended levels. The reference voltage

level V

negative input. The C1 capacitor should be located as close

as possible to the input pin.

VCC(or VDD)

CLK_IN

PCLK

nPCLK

VBB

Figure 1B shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF ~ V

generated by the bias resistors R1, R2 and C1.This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

and R2/R1 = 0.609.

VCC

R2

1K

V_REF

C1

0.1u

R1

1K

Single Ended Clock Input

PCLK

nPCLK