853111AY

www.icst.com/products/hiperclocks.html

REV. D JULY 22, 2003

7

Integrated

Circuit

Systems, Inc.

ICS853111

PRELIMINARY

Figure 2A shows an example of the differential input that can

be wired to accept single ended LVCMOS levels. The reference

voltage level V

the negative input. The C1 capacitor should be located as close

as possible to the input pin.

Figure 2B shows an example of the differential input that can

be wired to accept single ended LVPECL levels. The reference

voltage level V

the negative input. The C1 capacitor should be located as close

as possible to the input pin.

CLK_IN

C1

0.1uF

VDD(or VCC)

+

-

VBB

VCC

R2

1K

V_REF

C1

0.1u

R1

1K

Single Ended Clock Input

PCLK

nPCLK