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SCIMX6QP6AVT2AB датащи(PDF) 82 Page - NXP Semiconductors

номер детали SCIMX6QP6AVT2AB
подробное описание детали  i.MX 6DualPlus/6QuadPlus Automotive Applications Processors
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
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SCIMX6QP6AVT2AB датащи(HTML) 82 Page - NXP Semiconductors

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i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018
82
NXP Semiconductors
Electrical Characteristics
4.12.4.3 SDR50/SDR104 AC Timing
Figure 41 depicts the timing of SDR50/SDR104, and Table 52 lists the SDR50/SDR104 timing
characteristics.
Figure 41.
SDR50/SDR104 Timing
Table 52. SDR50/SDR104 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
Clock Frequency Period
tCLK
4.8
—
ns
SD2
Clock Low Time
tCL
0.46
× tCLK
0.54
× tCLK
ns
SD3
Clock High Time
tCH
0.46
× tCLK
0.54
× tCLK
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)
SD4
uSDHC Output Delay
tOD
–3
1
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)
SD5
uSDHC Output Delay
tOD
–1.6
0.74
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)
SD6
uSDHC Input Setup Time
tISU
2.5
—
ns
SD7
uSDHC Input Hold Time
tIH
1.5
—
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)1
1Data window in SDR100 mode is variable.
SD8
Card Output Data Window
tODW
0.5
× tCLK
—ns
Output from uSDHC to card
Input from card to uSDHC
SCK
SD4
SD3
SD5
SD3
SD8
SD7
SD6
SD1
SD2



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