844004AGI-04

www.icst.com/products/hiperclocks.html

REV. A JANUARY 26, 2006

8

Integrated

Circuit

Systems, Inc.

ICS844004I-04

PRELIMINARY

A general LVDS interface is shown in Figure 3. In a 100

Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100

Ω across near

the receiver input. For a multiple LVDS outputs buffer, if

only partial outputs are used, it is recommended to termi-

nate the unused outputs.

R1

100

3.3V

100 Ohm Differential Transmission Line

3.3V

+

-

LVDS

For applications not requiring the use of the crystal oscillator

input, both XTAL_IN and XTAL_OUT can be left floating.

Though not required, but for additional protection, a 1k

Ω

resistor can be tied from XTAL_IN to ground.

For applications not requiring the use of a clock input, it can

be left floating. Though not required, but for additional

protection, a 1k

Ω resistor can be tied from the CLK input to

ground.

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

LVDS

All unused LVDS outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential

output pair should either be left floating or terminated.